As semiconductor devices have become more highly integrated, the integration density of semiconductor devices has progressively increased. Because integration density is limited by the area of the device and the ability to form patterns within that area, there is a need for new methods that are capable of producing finer, more precise patterns than are possible using conventional techniques.
Fin field effect transistors (FINFETs) have been developed as one means of increasing the integration density of semiconductor devices. As sizes of FINFET devices have been reduced to 20 nm or less, it has become increasingly difficult to form isolation insulating layers in fin regions using conventional patterning methods, such as those discussed in U.S. Patent Publication No. 2013/0187237.
The inventive concepts provide structures and methods for producing finer, more precise patterns by preventing the misalignment of photolithography processes and insulating fin regions from each other in a lateral direction.